`timescale 1ns / 1ns

module tb();

parameter PERIOD  = 10;
reg           clk=1;
reg           rst_n=1;
reg[29:0]     din_data;
wire[32:0]    dout_data;
wire           dout_vld;



initial begin
    forever #(PERIOD/2)  clk=~clk;
end



initial begin
    $monitor ("din_data=%0b dout_vld=%0b",din_data, dout_vld);
    rst_n  =  0;
    #(PERIOD*2)
    rst_n  =  1;
    din_data <= 0;
    #(PERIOD*100)
    din_data <= 1;
    #(PERIOD*100)
    din_data <= 123;
    rst_n  =  0;
    #(PERIOD*2)
    rst_n  =  1;
    #(PERIOD*100)
    din_data <= 456;
    rst_n  =  0;
    #(PERIOD*2)
    rst_n  =  1;
    #(PERIOD*100)
    din_data <= 12345678;
    rst_n  =  0;
    #(PERIOD*2)
    rst_n  =  1;
    #(PERIOD*100)
    din_data <= 958;
    rst_n  =  0;
    #(PERIOD*2)
    rst_n  =  1;
    #(PERIOD*50);
end


binary2bcd  u_binary2bcd(
    .clk            (clk),
    .rst_n          (rst_n),
    .din_data              (din_data),
    .dout_data          (dout_data),
    .dout_vld(dout_vld)
    );

endmodule

